.. (לתיקייה המכילה) | ||
Q: What are the sources of a branch instruction? | |
A: The destination register of the last ALU operation. For example: sub r1, r2, r3 beq L1 beq has one src - r1 |
Q: When does an instruction removed from the RS? | |
A: in the end of the EXE stage |
Q: When does an allocation of new commands occurs after a flush? | |
A: After the branch instruction retires (can read more about it in the lecture - slide 50 and beyond) |
Q: In question 3, there must be chronological order between the sections? | |
A: No. |
Q: If a certain part of the processor is needed by two instructions at the same time (e.g. a ROB entry), | |
A: Yes, and in this case adding more entries to the ROB will be considered a solution to the hazard, even if the overall performance won’t improve due to other reasons. |