.. (לתיקייה המכילה) | ||
Q: In Q3, what can we add to the pipe? | |
A: It is recommended to add additional stages to the pipeline, and any components you wish. |
Q: Is pipeline MIPS, do we have register file split? | |
A: In general, in HW1, the pipeline has register file split. However, in Q2 section ב, the register file does not support a split, so you CANNOT use it. |
Q: In Q2 section א-b, what happens if we have two memory instructions one after the other (so the first is in MEM2 while the second is in MEM1)? | |
A: The second instruction doesn't "see" the effects of the first instruction, because the second instruction enters MEM1 before the first instruction finishes MEM2 (unless we stall the second instruction). |