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.. (לתיקייה המכילה) | |
when we write, because of the WT policy - we write to L1,L2 and the memory. | |
the first level that contains the data. L1HIT, if the data is in L1 (even if the block exist in L2 as well). L2HIT, if there is L1 write miss and L2 write Hit MEMACC, if there is a write miss for both caches. |
if there is L1 hit, should we update the L2 LRU? | |
the L1 and L2 LRU are diffrent. we update the L2 LRU only when there is an actual access to L2 (both read & write access). |
in inclusive cache, when we have an L2 read miss , what happends first: we invalidate an L1 line because it was evacuated from L2 or we evacuate a line from L1 because of LRU? | |
follow the example in the tutorial 9. we first invalidate in L1 due to L2 evacuation. this is important because you might not need to evacuate another line from L1 due to LRU policy, because the new block will just replace the invalidated one. |
if after an access, we want to add a block to a set that contains invalid line, | |
yes |