 |
.. (לתיקייה המכילה) | |
Do fetched instructions go into the cache? Should we count their misses? | |
|
Preferably no, but if you did otherwise, mark in your submission. Both solutions will accepted. |
Are memory accesses aligned to 2 bytes? | |
| Yes. You can assume all memory accesses are aligned to 2 bytes. |
IncreaseMisses does not do what it is supposed to do! | |
| There was a bug in the previous version. Either fix it or download the updated version. |
If we work in write-no-allocate, does it mean we use write-through? | |
| Yes. No miss on writes on this case. Remember to update LRU correctly, though. |
Can we get an example in and out? | |
|
You are expected to build your own tests to check your code. It will not be checked with big cache configurations or very complicated sources, just as previous assignments. As a very brief example: multiply.asm with the following parameters: #define CACHE_NUM_WAYS (1<<0) #define CACHE_DATA_SIZE (1<<4) #define CACHE_WRITE_ALLOCATE (true) #define CACHE_LINE_SIZE (1<<2) results in 2 misses without counting fetch misses, and 8 when they are. |
If the memory location is found in the cache should we update the LRUs? | |
| Of course. |
Can we choose how to determine which set a memory address maps to or is there a required format? | |
| No. It's always the LSBs (least-significant bits) above the offset in the line. |